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An efficient low area implementation of 2-D DCT on FPGA

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dc.contributor.authorDoğan, Atakan
dc.contributor.orcid0000-0002-1117-9689
dc.date.accessioned2025-11-13T11:35:05Z
dc.date.issued2015-11-01
dc.identifier.doihttps://doi.org/10.1109/eleco.2015.7394534
dc.identifier.openalexW2284257956
dc.identifier.urihttps://hdl.handle.net/11421/7280
dc.identifier.urihttps://doi.org/10.1109/eleco.2015.7394534
dc.language.isoen
dc.rightsrestrictedAccess
dc.subjectDiscrete cosine transform
dc.subjectField-programmable gate array
dc.subjectTranspose
dc.subjectComputer science
dc.subjectComputer hardware
dc.subjectImage (mathematics)
dc.subjectComputer vision
dc.subject.sdg9
dc.titleAn efficient low area implementation of 2-D DCT on FPGA
dc.typeArticle
dspace.entity.typePublication
local.authorid.openalexA5070030139

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